Register Hardware

Original URL: http://www.reghardware.co.uk/2007/04/12/ibm_chip_stack_technique/

Big Blue boffins build 3D chip stack tech

By Tony Smith
Published Thursday 12th April 2007 10:30 GMT

IBM is bidding to become the NCP (http://www.ncp.co.uk/) of semiconductors with a multi-storey chip technology that it hopes will allow CPUs to be stacked with memory, specialised processing cores and other components one on top of the other.

Mounting chip components vertically is nothing new, but the new IBM technique abandons the wires typically used to connect stacked chip dice and replaces them with metal links formed by drilling through each die's silicon and filling the holes with metal. These in-silicon pins are dubbed 'through-silicon vias' by IBM's boffins.

It's a trick that reduces the distance die-to-die signals need to travel by a factor of 1000 and enables a hundredfold increase in the number of links that can be established between dice, IBM claimed.

IBM 'through-silicon via' stacked chips

The upshot: cores can be physically packed closer together and are able to exchange information much more quickly. They may also form a more efficient way of channelling heat up through the stack to the package's cooling system - which may already have been made more effective through the novel canal-based package surface (http://www.reghardware.co.uk/2007/03/22/ibm_paste_spreading_scheme/) IBM announced last month. Multi-core processors using through-silicon vias could consume 20 per cent less energy, the company suggested.

IBM said the new technique will be used in mass-produced chips in 2008, with sample product going out to its customers during the latter half of this year to help them evaluate it.